1. Field of the Invention
The present invention relates to phase lock loops, more particularly to phase lock loops having both a wide-band mode and a narrow-band mode of operation.
2. State of the Art
Practically all modem signal generators and radio communications equipment use digital frequency synthesizers based on the phase locked loop (PLL). The realization of the PLL in an integrated circuit has led to the widespread adoption of inexpensive frequency synthesizers. In its application of frequency synthesis (as opposed to signal detection), the input signal-to-noise ratio of the PLL is high, and the PLL serves to lock the output frequency on a multiple of the input frequency.
A PLL consists generally of three parts: a reference frequency input portion, a loop filter portion, and a voltage-controlled oscillator (VCO) portion. The reference frequency portion includes a phase comparator and may include a frequency divider (which may be programmable). The phase comparator compares an output signal of the PLL with the reference frequency itself or the reference frequency divided down, thereby producing an error signal. The loop filter filters the error signal to produce a control signal that is applied to the VCO. During proper operation, the control signal drives the VCO in the proper direction so as to cause the error signal to be driven to zero or nearly zero.
PLLs generally operate in two different modes: acquisition during which the PLL locks onto a particular frequency, and tracking, during which the PLL ensures that it remains locked. Both fast acquisition and accurate tracking in the presence of modulation are important design objectives. Unfortunately, these design objectives are, in general, conflicting. For fast acquisition, a wide loop bandwidth is desired. For accurate tracking, in the presence of modulation, a narrow loop bandwidth is desired. In cellular applications, for example, when changing channels, a wide loop bandwidth is desired to accomplish the frequency change as quickly as possible. When operating on a single channel, voice data having low frequency content is modulated onto a carrier signal. The PLL attempts in effect to cancel the modulation, which appears to the PLL as frequency drift. To accomplish slow modulation, therefore, a very narrow loop bandwidth is desired, such that the modulation is accomplished outside the PLL bandwidth.
One proposal has been to, in narrowband mode, open the loop entirely during short modulation bursts and to close the loop when modulation is not applied. This approach assumes that, if the loop is opened for only short periods at a time, the drift that may occur during open-loop operation will not be substantial. This solution may be acceptable under certain limited conditions but is not generally applicable.
Referring more particularly to FIG. 1, a portion of a PLL is shown, including the loop filter and the VCO. The loop filter includes a charge pump having a first "pump-up" current source connected to inject current into circuit node A, and a second "pump-down" current source connected to withdraws current from the same node. The pump-up current source is connected to a positive supply voltage V+, and the pump-down current source is connected to a negative supply voltage V-. Besides the charge pump, there is also connected to node A a loop filter, typically realized by a capacitor connected to ground and the series combination of a resistor and capacitor, connected to ground. A tuning voltage VT is produced at node A and is input to the VCO to control the rate of oscillation of the VCO.
The loop bandwidth of the circuit of FIG. 1 may be changed by changing the values of one or both of the capacitors, such that they charge more slowly or more quickly. Changing the values of the capacitors usually requires some form of switching. However, it is also important not to disturb the voltage on the capacitors. Switching usually introduces undesirable transients, since it is well-known that to change a capacitor value at a fixed voltage requires an instantaneous change in the stored charge. A preferable way of changing the loop bandwidth then is to vary the magnitude of the currents supplied by the current sources. To switch from wide to narrow bandwidth, for example, instead of switching in additional capacitors to make the capacitance larger, the current gain would be altered to make the currents smaller.
U.S. Pat. No. 5,675,292 describes a PLL that enables smooth switching of loop bandwidth over a wide range. By switchably inserting a resistance between the output of a current-mode charge pump and a loop filter of the PLL, current sources of the charge pump are made to appear as voltage sources, and a suitably small trickle current may be obtained for narrowband tracking. During acquisition, the resistance is bypassed, such that the current sources again function as current sources in the PLL for fast loop response. Typically, another switch is required to adjust the dynamic characteristics of the loop filter. Operation is not entirely free of transients.
What is needed, then, is an improved PLL that enables smooth switching of loop bandwidth.